US 12,457,751 B2
Interfacial layer with high texture uniformity for ferroelectric layer enhancement
Tzu-Yu Chen, Kaohsiung (TW); Sheng-Hung Shih, Hsinchu (TW); Fu-Chen Chang, New Taipei (TW); and Kuo-Chi Tu, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 11, 2022, as Appl. No. 17/572,919.
Claims priority of provisional application 63/223,176, filed on Jul. 19, 2021.
Prior Publication US 2023/0017020 A1, Jan. 19, 2023
Int. Cl. H10B 53/30 (2023.01); H01L 23/48 (2006.01); H10D 64/68 (2025.01); H10D 84/80 (2025.01)
CPC H10B 53/30 (2023.02) [H01L 23/481 (2013.01); H10D 64/689 (2025.01); H10D 84/80 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a bottom electrode layer over a substrate;
depositing a first interfacial layer overlying the bottom electrode layer;
depositing a ferroelectric layer overlying and directly on the first interfacial layer;
depositing a top electrode layer overlying the ferroelectric layer;
performing a first etch into the top electrode layer to form a top electrode;
performing a second etch into the ferroelectric layer, the first interfacial layer, and the bottom electrode layer; and
forming a sidewall spacer structure on a sidewall of the top electrode between the first etch and the second etch;
wherein a top surface of the first interfacial layer has greater texture uniformity than a top surface of the bottom electrode layer.