US 12,457,749 B2
Three-dimensional memory device with backside support pillar structures and methods of forming the same
Akihiro Tobioka, Nagoya (JP)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Feb. 15, 2024, as Appl. No. 18/442,792.
Application 18/524,552 is a division of application No. 17/146,866, filed on Jan. 12, 2021, granted, now 11,844,222, issued on Dec. 12, 2023.
Application 18/442,792 is a continuation of application No. 18/524,552, filed on Nov. 30, 2023, granted, now 12,408,345.
Prior Publication US 2024/0292628 A1, Aug. 29, 2024
Int. Cl. H10B 43/50 (2023.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H10B 41/27 (2023.01); H10B 41/50 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/50 (2023.02) [H01L 23/5226 (2013.01); H01L 23/562 (2013.01); H10B 41/27 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A three-dimensional memory device, comprising:
alternating stacks of insulating layers and electrically conductive layers, wherein the alternating stacks are laterally spaced apart from each other by backside isolation assemblies that generally laterally extend along a first horizontal direction through entire heights of the alternating stacks with lateral undulations along a second horizontal direction that is perpendicular to the first horizontal direction, and wherein each of the alternating stacks has a modulation in width along the second horizontal direction as a function of a position along the first horizontal direction; and
memory stack structures that vertically extend through a respective one of the alternating stacks, and wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements,
wherein each of the backside isolation assemblies comprises a respective laterally alternating sequence of backside dielectric isolation walls and dielectric support pillar structures such that a subset of the dielectric support pillar structures is in direct contact with a respective pair of backside dielectric isolation walls of the backside dielectric isolation walls; and
wherein at least one of the dielectric support pillar structures has a respective pair of lateral indentations that is filled by end portions of a respective pair of backside dielectric isolation walls of the backside dielectric isolation walls.