| CPC H10B 43/40 (2023.02) [H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H10B 43/27 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a first structure having a first memory region, a second memory region, and an extension region between the first memory region and the second memory regions, the first structure including word lines spaced apart from each other; and
a second structure having a circuit region overlapping the extension region in a vertical direction perpendicular to an upper surface of the second structure,
wherein:
the word lines include a first common word line and a second common word lines disposed at different height levels relative to the upper surface of the second structure, and a first intermediate individual word line and a second intermediate individual word lines disposed at a first same height level relative to the upper surface of the second structure and spaced apart from each other,
each of the first common word line and the second common word line is disposed in the first memory region, the extension region, and the second memory region,
the first intermediate individual word line is disposed in the first memory region and extends into the extension region, wherein the first intermediate individual word line is disposed at a height level that is between the different height levels of the first common word line and the second common word line,
the second intermediate individual word line is disposed in the second memory region and extends into the extension region,
the circuit region includes pass transistors electrically connected to the word lines,
the pass transistors include common transistors and individual transistors, and
at least one of the common transistors and at least one of the individual transistors overlap the word lines in the extension region.
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