| CPC H10B 43/27 (2023.02) [H10B 51/20 (2023.02); H10B 63/34 (2023.02)] | 4 Claims |

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1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising a set of dielectric-metal-oxide blocking dielectric portions located at levels of the electrically conductive layers, a memory material layer, and a vertical semiconductor channel,
wherein:
each of the electrically conductive layers comprises a tubular metal nitride portion and a metal fill material portion;
each of the tubular metal nitride portions of the electrically conductive layers laterally surrounds and contacts a respective one of the dielectric-metal-oxide blocking dielectric portions;
each metal fill material portion either contacts respective overlying and underlying insulating layers of the insulating layers, or contacts respective upper and lower metal nitride liner portions which have a smaller thickness than the tubular metal nitride portions; and
the set of dielectric-metal-oxide blocking dielectric portions comprise discrete dielectric-metal-oxide blocking dielectric portions each of which comprises a respective cylindrical outer sidewall that vertically extends from a respective underlying insulating layer of the insulating layers to a respective overlying insulating layer of the insulating layers, an annular top surface in contact with the respective overlying insulating layer, and an annular bottom surface in contact with the respective underlying insulating layer.
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