| CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] | 11 Claims |

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1. A three-dimensional memory device, comprising:
a pair of layer stacks laterally extending along a first horizontal direction and laterally spaced from each other along a second horizontal direction by a backside trench, wherein each of the layer stacks comprises a first-tier alternating stack of first insulating layers and first electrically conductive layers, a first insulating cap layer located over the first-tier alternating stack, and a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the first insulating cap layer;
memory openings vertically extending through the pair of layer stacks;
memory opening fill structures located in the respective memory openings and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel;
a bridge structure spanning an entire width of the backside trench along the second horizontal direction, wherein a top surface of the bridge structure is located in a first horizontal plane disposed below top surfaces of the second-tier alternating stacks, and a bottom surface of the bridge structure is located in a second horizontal plane disposed above bottom surfaces of the first-tier alternating stacks; and
a backside trench fill structure located in the backside trench,
wherein:
a combination of the backside trench fill structure and the first insulating cap layers embeds the bridge structure; and
the bridge structure comprises a pair of first sidewalls that contact the first insulating cap layers within the pair of layer stacks, and comprises a top surface located within a horizontal plane including top surfaces of the first insulating cap layers.
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