US 12,457,741 B2
Memory device including composite metal oxide semiconductor channels and methods for forming the same
Peter Rabkin, Cupertino, CA (US); and Masaaki Higashitani, Cupertino, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on May 3, 2022, as Appl. No. 17/661,783.
Prior Publication US 2023/0363158 A1, Nov. 9, 2023
Int. Cl. H10B 43/27 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising a memory die, the memory die comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising a memory film and a vertical composite metal oxide semiconductor channel comprising a different composition between its inner and outer portions;
wherein the vertical composite metal oxide semiconductor channel comprises an indium tin zinc oxide layer in the outer portion, and an indium gallium zinc oxide layer in the inner portion; and
wherein the vertical composite metal oxide semiconductor channel further comprises an indium gallium tin zinc oxide layer located between the indium tin zinc oxide layer and the indium gallium zinc oxide layer.