US 12,457,739 B2
Semiconductor memory device
Takamasa Ito, Nagoya (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Oct. 11, 2023, as Appl. No. 18/484,492.
Application 18/484,492 is a continuation of application No. 16/798,577, filed on Feb. 24, 2020, granted, now 11,818,885.
Claims priority of application No. 2019-168704 (JP), filed on Sep. 17, 2019.
Prior Publication US 2024/0040782 A1, Feb. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 41/27 (2023.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 5/025 (2013.01); G11C 5/06 (2013.01); H10B 43/27 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a first conductive layer;
a plurality of second conductive layers provided above the first conductive layer and stacked in a first direction;
a first semiconductor layer extending in the first direction in the plurality of second conductive layers and being in contact with the first conductive layer;
a charge storage layer arranged between the first semiconductor layer and the plurality of second conductive layers;
a second semiconductor layer extending in the first direction and a second direction intersecting the first direction above the first conductive layer, and separating the plurality of second conductive layers in a third direction intersecting the first direction and the second direction; and
a first insulating layer provided between the second semiconductor layer and the first conductive layer and between the second semiconductor layer and the plurality of second conductive layers, the first insulating layer provided below an entirety of the second semiconductor layer in a cross section along the first direction and the third direction, wherein
the second semiconductor layer is not in contact with the first conductive layer.