US 12,457,738 B2
Three-dimensional memory device containing engineered charge storage elements and methods for forming the same
Rahul Sharangpani, Fremont, CA (US); Raghuveer S. Makala, Campbell, CA (US); Adarsh Rajashekhar, Santa Clara, CA (US); and Fei Zhou, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Jul. 12, 2023, as Appl. No. 18/351,205.
Claims priority of provisional application 63/428,574, filed on Nov. 29, 2022.
Prior Publication US 2024/0179897 A1, May 30, 2024
Int. Cl. H10B 41/27 (2023.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 41/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
an alternating stack comprising a plurality of insulating layers and a plurality of electrically conductive layers;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film, wherein the memory film comprises:
a tunneling dielectric layer;
a continuous charge storage material layer extending through the alternating stack and being continuous between vertical levels of the electrically conductive layers of the plurality of electrically conductive layers;
a vertical stack of a plurality of discrete charge storage elements, each discrete charge storage element of the plurality of discrete charge storage elements is located at a vertical level of a respective electrically conductive layer of the plurality of electrically conductive layers and having a first sidewall facing a center of the memory opening and directly contacting a respective surface segment of an outer sidewall of the continuous charge storage material layer; and
a discontinuous blocking dielectric material layer comprising a vertical stack of a plurality of discrete blocking dielectric material portions comprising silicon atoms and oxygen atoms and vertically spaced apart from each other, each discrete blocking dielectric material portion of the plurality of discrete blocking dielectric material portions is located at the vertical level of a respective electrically conductive layer of the plurality of electrically conductive layers,
wherein the plurality of discrete charge storage elements are floating gates.