US 12,457,737 B2
Three-dimensional memory device containing on-pitch drain select level structures and methods of making the same
Kanta Watanabe, Yokkaichi (JP); and Yanli Zhang, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Sep. 21, 2022, as Appl. No. 17/933,969.
Application 17/933,969 is a continuation in part of application No. 17/126,504, filed on Dec. 18, 2020, granted, now 11,968,825.
Application 17/126,504 is a continuation in part of application No. PCT/US2019/020127, filed on Feb. 28, 2019.
Application PCT/US2019/020127 is a continuation of application No. 16/019,821, filed on Jun. 27, 2018, granted, now 10,475,804, issued on Nov. 12, 2019.
Application PCT/US2019/020127 is a continuation of application No. 16/019,856, filed on Jun. 27, 2018, granted, now 10,600,800, issued on Mar. 24, 2020.
Prior Publication US 2023/0013725 A1, Jan. 19, 2023
Int. Cl. H10B 41/27 (2023.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01)
CPC H10B 41/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 30/6891 (2025.01); H10D 30/694 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and word-line-level electrically conductive layers;
a vertical layer stack located over the alternating stack, the vertical layer stack comprising multiple levels of drain select electrodes and multiple levels of drain-select-level insulating layers that are vertically interlaced;
a spacer insulating layer located between the alternating stack and the vertical layer stack, the spacer insulating layer having a thickness which is greater than a thickness of each of the respective insulating layers in the alternating stack, and is greater than a thickness of each of the respective drain-select-level insulating layers;
drain-select-level isolation structures laterally extending along a first horizontal direction such that drain select electrodes located at a same level are laterally spaced apart from each other by the drain-select-level isolation structures;
memory openings vertically extending through the vertical layer stack, the spacer insulating layer, and the alternating stack; and
memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, wherein the three-dimensional memory device further comprises at least one feature selected from:
a first feature wherein each of the drain-select-level isolation structures is in direct contact with a respective drain select electrode at each of the levels of the drain select electrodes; or
a second feature wherein three-dimensional memory device further comprises a contact-level dielectric layer overlying the vertical layer stack and drain contact via structures vertically extending through the contact-level dielectric layer, wherein: top surfaces of the drain-select-level isolation structures are located within a horizontal plane including a top surface of the contact-level dielectric layer; each of the memory opening fill structures comprises a respective drain region; and top surfaces of the drain contact via structures are located within the horizontal plane including the top surface of the contact-level dielectric layer.