| CPC H10B 41/27 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 11 Claims |

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1. A semiconductor structure, comprising:
an alternating stack of insulating layers and electrically conductive layers;
memory openings vertically extending through the alternating stack;
memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective vertical stack of memory elements;
a dielectric material portion;
contact via structures vertically extending through the dielectric material portion and contacting a respective one of the electrically conductive layers;
an integrated via and pad structure comprising a conductive via portion vertically extending through the dielectric material portion and contacting a front side of a conductive pad portion; and
a backside contact pad structure contacting a planar backside surface of the integrated via and pad structure;
wherein each of the contact via structures comprises a first base metal portion in contact with the respective one of the electrically conductive layers, a first metallic liner in contact with the first base metal portion, and a first metallic fill material portion that is laterally surrounded by the first metallic liner and vertically spaced from the first base metal portion by a horizontally-extending portion of the first metallic liner.
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