| CPC H10B 41/20 (2023.02) [H01L 21/02164 (2013.01); H01L 21/0228 (2013.01); H10D 84/0133 (2025.01); H10D 84/038 (2025.01)] | 21 Claims |
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1. A method for forming two transistor cells for vertical three-dimensional (3D) memory comprising:
depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material, in repeating iterations vertically to form a vertical stack on a substrate;
forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack and extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack;
conformally depositing a first conductive material on a gate dielectric material in the plurality of first vertical openings;
removing portions of the first conductive material in the plurality of first vertical openings to form a plurality of separate, vertical access line pairs along the sidewalls of the elongated vertical, pillar columns, wherein:
the pairs of vertically oriented access lines are orthogonal to the substrate;
a first vertical access line pair is located between a horizontally oriented digit line and a second vertical access line pair, wherein the horizontally oriented digit line is parallel to the substrate; and
the second vertical access line pair is located between the first vertical access line pair and a source line, wherein:
an independent source/drain region of a first transistor of a memory cell is coupled to a respective horizontally oriented digit line and an independent source/drain region of a second transistor of the memory cell is coupled to a respective common source line;
each respective common source line is parallel to the substrate; and
each respective common source line is coupled to only a single row of memory cells;
forming second vertical openings through the vertical stack and extending predominantly in the first horizontal direction to expose second vertical sidewalls adjacent first regions of the semiconductor material on opposite sides of the vertical access line pairs of the elongated vertical, pillar columns;
selectively etching the second dielectric material to form first horizontal openings, wherein the second dielectric material is removed a first distance (DIST 1) horizontally back from the second vertical openings;
gas phase doping a dopant in a top surface of the semiconductor material in the first horizontal openings to form source/drain regions;
forming a conductive material onto the top surface above the source/drain regions in the first horizontal openings;
selectively etching the conductive material, the source/drain regions and a first portion of a low doped semiconductor material beneath the source/drain regions to form second horizontal openings having a second distance (DIST 2) horizontally back from the second vertical openings; and
depositing a third dielectric material in second horizontal openings laterally adjacent the conductive material and the source/drain regions.
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