| CPC H10B 12/30 (2023.02) [G11C 5/10 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01)] | 10 Claims |
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1. A memory cell comprising:
a first wiring;
a first transistor comprising a first gate over the first wiring, a first oxide semiconductor over the first gate, a first source and a first drain electrically connected to the first oxide semiconductor, and a second gate over the first oxide semiconductor;
a second transistor comprising a third gate over the second gate, a second oxide semiconductor over the third gate, a second source and a second drain electrically connected to the second oxide semiconductor, and a fourth gate over the second oxide semiconductor;
a second wiring over the fourth gate; and
a capacitor,
wherein one of the first source and the first drain is electrically connected to the first wiring,
wherein one of the second source and the second drain is electrically connected to the second wiring,
wherein the other of the second source and the second drain is electrically connected to the second gate and a first electrode of the capacitor,
wherein data is configured to be written to the memory cell through the second wiring, and
wherein data held in the memory cell is configured to be read out through the first wiring.
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