US 12,457,685 B2
Circuit board, light-emitting substrate, backlight module, and display apparatus
Nianqi Yao, Beijing (CN); Kun Zhao, Beijing (CN); Ce Ning, Beijing (CN); Zhengliang Li, Beijing (CN); Zhanfeng Cao, Beijing (CN); Ke Wang, Beijing (CN); Jiaxiang Zhang, Beijing (CN); Qi Qi, Beijing (CN); Hehe Hu, Beijing (CN); Feifei Li, Beijing (CN); Jie Huang, Beijing (CN); and Jiayu He, Beijing (CN)
Assigned to Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 18/552,754
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Oct. 31, 2022, PCT No. PCT/CN2022/128740
§ 371(c)(1), (2) Date Sep. 27, 2023,
PCT Pub. No. WO2024/092439, PCT Pub. Date May 10, 2024.
Prior Publication US 2025/0098064 A1, Mar. 20, 2025
Int. Cl. H05K 1/02 (2006.01); G02F 1/1335 (2006.01); G02F 1/13357 (2006.01); H05K 1/11 (2006.01); H05K 3/28 (2006.01)
CPC H05K 1/0298 (2013.01) [G02F 1/133603 (2013.01); G02F 1/133612 (2021.01); H05K 1/116 (2013.01); H05K 3/282 (2013.01); H05K 2201/10106 (2013.01); H05K 2201/2054 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit board, comprising:
a substrate;
a first conductive layer disposed on a side of the substrate; the first conductive layer including a plurality of signal lines and a plurality of first conductive portions;
a first insulating layer disposed on a side of the first conductive layer away from the substrate; the first insulating layer being provided with first via holes extending through the first insulating layer; and
a second conductive layer disposed on a side of the first insulating layer away from the substrate; the second conductive layer including a plurality of second conductive portions; a second conductive portion passing through a first via hole to be in electrical contact with a first conductive portion; the second conductive portion including a plurality of pads, and a pad being a portion of the second conductive portion exposed by the first via hole in the first insulating layer; wherein
the first conductive layer and the second conductive layer each include at least one main conductive layer, and the main conductive layer is configured to be capable of creating a first intermetallic compound with solder; at least one of the first conductive layer and the second conductive layer further includes a stop layer, and the stop layer is disposed between two adjacent main conductive layers and is configured to be capable of creating a second intermetallic compound with the solder; and a rate of a reaction between the stop layer and the solder is lower than a rate of a reaction between the main conductive layer and the solder.