US 12,457,684 B2
Eddy current mitigation for on-chip inductors
Behzad Biglarbegian, San Jose, CA (US); Hongrui Wang, San Jose, CA (US); Abbas Komijani, Mountain View, CA (US); and Reetika K Agarwal, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 26, 2023, as Appl. No. 18/474,880.
Application 18/474,880 is a continuation of application No. 18/303,486, filed on Apr. 19, 2023.
Prior Publication US 2024/0357734 A1, Oct. 24, 2024
Int. Cl. H05K 1/02 (2006.01); H01P 3/08 (2006.01)
CPC H05K 1/0243 (2013.01) [H01P 3/08 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/1003 (2013.01); H05K 2201/10075 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a substrate;
an inductor on the substrate;
a first tree of capacitors on the substrate and overlapping the inductor; and
a second tree of capacitors on the substrate and overlapping the inductor.