US 12,457,683 B2
Eddy current mitigation for on-chip inductors
Behzad Biglarbegian, San Jose, CA (US); Hongrui Wang, San Jose, CA (US); Abbas Komijani, Mountain View, CA (US); and Reetika K Agarwal, Sunnyvale, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Apr. 19, 2023, as Appl. No. 18/303,486.
Prior Publication US 2024/0357733 A1, Oct. 24, 2024
Int. Cl. H05K 1/02 (2006.01); H01P 3/08 (2006.01)
CPC H05K 1/0243 (2013.01) [H01P 3/08 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/1003 (2013.01); H05K 2201/10075 (2013.01)] 20 Claims
OG exemplary drawing
 
1. Circuitry comprising:
a substrate;
an inductor layered on the substrate, wherein the inductor comprises a loop that laterally surrounds a first region of the substrate;
a ring of ground traces on the substrate and extending around the inductor and a second region of the substrate, the ring of ground traces being laterally separated from the inductor by the second region of the substrate;
first capacitors layered on the substrate and overlapping the second region of the substrate; and
second capacitors layered on the substrate and overlapping the first region of the substrate.