US 12,457,682 B2
Crosstalk cancellation for signal lines
M. Ataul Karim, Boise, ID (US); David K. Ovard, Meridian, ID (US); Aparna U. Limaye, Boise, ID (US); and Timothy M. Hollis, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 10, 2024, as Appl. No. 18/632,122.
Application 18/632,122 is a division of application No. 17/238,797, filed on Apr. 23, 2021, granted, now 11,979,979.
Prior Publication US 2024/0260171 A1, Aug. 1, 2024
Int. Cl. H05K 1/02 (2006.01); H04B 3/32 (2006.01); H04B 3/487 (2015.01)
CPC H05K 1/0233 (2013.01) [H04B 3/32 (2013.01); H04B 3/487 (2015.01); H05K 1/0228 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first ground plane extending in a first direction and a second direction;
a second ground plane parallel to the first ground plane;
a set of signal lines couplable with a host device for a memory device, wherein each signal line of the set of signal lines:
extends in the first direction between the first ground plane and the second ground plane;
overlaps with a first other signal line of the set of signal lines along the second direction; and
overlaps with a second other signal line of the set of signal lines along a third direction that is orthogonal to the first direction and the second direction; and
circuitry configured to:
transmit a first signal via a first signal line of the set of signal lines;
transmit a second signal via a second signal line of the set of signal lines; and
transmit a third signal via the second signal line, the third signal for combining with a fourth signal on the second signal line to obtain a fifth signal via the second signal line with a lower amplitude than each of the third signal and the fourth signal, and the fourth signal based at least in part on the first signal and a capacitance between the first signal line and the second signal line.