| CPC H04W 72/23 (2023.01) [H04L 5/0032 (2013.01); H04W 24/08 (2013.01); H04W 48/12 (2013.01); H04W 72/0446 (2013.01); H04W 72/0453 (2013.01); H04W 72/0466 (2013.01); H04W 72/535 (2023.01); H04W 76/11 (2018.02); H04W 76/27 (2018.02); H04W 80/02 (2013.01)] | 28 Claims |

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8. A wireless device comprising:
one or more processors; and
memory storing instructions that, when executed by the one or more processors, cause the wireless device to:
based on an active bandwidth part (BWP) of a secondary cell being a dormant BWP during a first time period, receive, via a primary cell, first downlink control information (DCI) comprising at least one first resource assignment for the primary cell; and
based on the active BWP of the secondary cell not being a dormant BWP during a second time period different from the first time period, receive, via the secondary cell, second DCI comprising at least one second resource assignment for the primary cell.
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