US 12,457,178 B2
NIC priority queue steering and processor unit frequency tuning based on packet flow analytics
David Coyle, Limerick (IE); Brendan Ryan, Westbury (IE); John J. Browne, Limerick (IE); Jeffery G. Oliver, Happy Valley, OR (US); Pallavi Manaji Kadam, Portland, OR (US); and Sunku Ranganath, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/359,303.
Prior Publication US 2021/0320881 A1, Oct. 14, 2021
Int. Cl. H04L 12/28 (2006.01); H04L 47/2441 (2022.01); H04L 47/263 (2022.01); H04L 47/625 (2022.01); H04L 47/628 (2022.01); H04L 47/6295 (2022.01); H04L 47/70 (2022.01); H04L 47/80 (2022.01); H04L 49/90 (2022.01)
CPC H04L 47/627 (2013.01) [H04L 47/2441 (2013.01); H04L 47/263 (2013.01); H04L 47/628 (2013.01); H04L 47/6295 (2013.01); H04L 47/805 (2013.01); H04L 47/822 (2013.01); H04L 49/90 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A system comprising:
a network interface controller comprising circuitry to:
determine per-flow analytics information for a plurality of packet flows that are received at the network interface controller and provided from the network interface controller to a plurality of processor units; and
facilitate differential rate processing by the plurality of processor units of a plurality of packet queues for the plurality of packet flows based on the per-flow analytics information, wherein a first packet flow of the plurality of packet flows is assigned to a first packet queue of the plurality of packet queues based upon sizes of packets of the first packet flow.