US 12,457,175 B2
Managing quality of service by allocating die parallelism with variable queue depth
Shirish Bahirat, Longmont, CO (US); Anand Ramalingam, Portland, OR (US); Solomon Sagar Albert Jayaraj, Gainesville, FL (US); Fnu Sachin, Blacksburg, VA (US); and Xin Guo, San Jose, CA (US)
Assigned to SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed by SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed on Jun. 23, 2021, as Appl. No. 17/355,915.
Prior Publication US 2021/0392083 A1, Dec. 16, 2021
Int. Cl. H04L 47/24 (2022.01)
CPC H04L 47/24 (2013.01) 17 Claims
OG exemplary drawing
 
1. A memory controller comprising:
one or more substrates; and
a logic coupled to the one or more substrates, where the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the logic to:
determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis, wherein the projected bandwidth levels and the projected quality of service levels are determined for a plurality of device configurations based on one or more storage device parameters, wherein the one or more storage device parameters include one or more of an internal queue depth, a media operation speed, a per die read projection, a per die write projection, a program suspend projection, or an erase suspend projection;
receive, from a host, a requested bandwidth level and a requested quality of service level in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels;
receive, from the host, a command priority in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels; and
control the internal queue depth to maintain the requested quality of service level, wherein the internal queue depth is controlled based at least in part on dynamically reallocating the command priority via the memory controller.