| CPC H04L 41/0803 (2013.01) [H04L 41/122 (2022.05)] | 21 Claims |

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8. A computing system comprising:
a memory;
a computing environment including a plurality of interconnected computing devices; and
a processor to:
in at least one node including an upper topology including a virtual ethernet device, a lower topology including a first virtual network device and a second virtual network device, and a control plane coupled between the upper topology and the lower topology, wherein the upper topology is decoupled from the lower topology:
direct communication between the first virtual network device and the virtual ethernet device through the control plane via a first receive path from the first virtual network device to the virtual ethernet device and a first transmit path from the virtual ethernet device to the first virtual network device;
establish a second receive path from the second virtual network device to the virtual ethernet device, such that the virtual ethernet device is able to receive communication from the first virtual network device and the second virtual network device;
disable the first transmit path from the virtual ethernet device to the first virtual network device;
establish a second transmit path from the virtual ethernet device to the second virtual network device; and
disable the first receive path from the first virtual network device to the virtual ethernet device.
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