US 12,457,089 B2
Communication apparatus and communication system
Toshihisa Hyakudai, San Diego, CA (US); Junya Yamada, Kanagawa (JP); and Satoshi Ota, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 18/264,112
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Feb. 3, 2022, PCT No. PCT/JP2022/004160
§ 371(c)(1), (2) Date Aug. 3, 2023,
PCT Pub. No. WO2022/172838, PCT Pub. Date Aug. 18, 2022.
Application 18/264,112 is a continuation of application No. 17/536,751, filed on Nov. 29, 2021, granted, now 11,743,024.
Claims priority of provisional application 63/148,022, filed on Feb. 10, 2021.
Prior Publication US 2024/0089074 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04B 3/00 (2006.01); G10L 19/02 (2013.01); H03L 7/18 (2006.01); H04L 7/00 (2006.01); H04L 7/06 (2006.01); H04L 25/00 (2006.01); H04L 69/22 (2022.01)
CPC H04L 7/0008 (2013.01) [G10L 19/02 (2013.01); H03L 7/18 (2013.01); H04L 7/06 (2013.01); H04L 69/22 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A communication apparatus comprising:
a counting section that counts a number of clocks of a reference clock included in one cycle of a divided signal of an audio master clock with a frequency that is equal to a product of a frequency of a sampling clock for sampling of an audio signal and a multiplier on a basis of the audio master clock, a ratio of division of the divided signal, and the reference clock; and
a packet generator that generates a packet including information including the number of clocks counted at the counting section, a bit width of Serial Data (SD) conforming to an Inter-IC Sound (I2S) standard, the frequency of the sampling clock, the ratio of division of the divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD.