US 12,456,985 B2
Noise filtering circuit, D/A converter, and electronic device including the same
Moo Yeol Choi, Seongnam-si (KR); Young Hyun Yoon, Gwangmyeong-si (KR); Hyun Sun Shim, Seongnam-si (KR); and Myung-Jin Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 14, 2024, as Appl. No. 18/663,352.
Application 18/663,352 is a continuation of application No. 17/815,678, filed on Jul. 28, 2022, granted, now 12,015,418.
Claims priority of application No. 10-2021-0176707 (KR), filed on Dec. 10, 2021.
Prior Publication US 2024/0297659 A1, Sep. 5, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 1/00 (2006.01); H03M 1/08 (2006.01)
CPC H03M 1/08 (2013.01) 20 Claims
OG exemplary drawing
 
1. A noise filtering circuit comprising:
a first amplifier configured to receive a bias voltage at a first input terminal, receive a bias output voltage through a feedback path at a second input terminal, and compensate for a difference between the bias voltage and the bias output voltage;
a first transistor connected to an output of the first amplifier;
a first capacitor connected to a first terminal of the first transistor;
a second capacitor connected to a second terminal of the first transistor and the second input terminal of the first amplifier;
a second transistor connected to the second capacitor and the second input terminal of the first amplifier; and
a second amplifier having a first input terminal connected to the first capacitor and a second input terminal connected to the second transistor.