US 12,456,982 B2
Clock and data recovery device
Young Jae Chang, Seoul (KR); Sung Ryong Lee, Seongnam-Si (KR); and Jae Sam Shim, Seoul (KR)
Assigned to SILICON MITUS, INC., Seongnam-Si (KR); and Silicon-Magic Semiconductor Technology (Hangzhou) Co., Ltd., Hangzhou (CN)
Filed by SILICON MITUS, INC., Seongnam-Si (KR); and Silicon-Magic Semiconductor Technology (Hangzhou) Co., Ltd., Hangzhou (CN)
Filed on Nov. 7, 2023, as Appl. No. 18/503,959.
Claims priority of application No. 10-2022-0146826 (KR), filed on Nov. 7, 2022.
Prior Publication US 2024/0154616 A1, May 9, 2024
Int. Cl. H03D 3/24 (2006.01); H03L 7/087 (2006.01); H03L 7/099 (2006.01); H03L 7/107 (2006.01)
CPC H03L 7/087 (2013.01) [H03L 7/0991 (2013.01); H03L 7/1075 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A clock and data recovery device that reduces loop delay in a bang-bang loop, the clock and data recovery device comprising:
an equalizer that compensates for channel loss of input data;
a phase detector that compares data output from the equalizer and a fed back clock and outputs an up signal and a down signal;
a charge pump that operates according to the up signal and the down signal to output a control signal;
a loop filter that removes a high-frequency component included in the control signal output from the charge pump;
a voltage-controlled oscillator that changes a frequency of the clock and outputs the clock according to the control signal from which the high-frequency component is removed; and
a voltage-controlled oscillator buffer that adjusts a slew rate of the clock output by the voltage-controlled oscillator according to the up signal and the down signal directly received from the phase detector and transmits the clock to the phase detector,
wherein the phase detector outputs the up signal when a phase of a clock fed back from the voltage-controlled oscillator buffer is slower than the data output by the equalizer, and outputs the down signal when the phase of the clock fed back from the voltage-controlled oscillator buffer is faster than the data output by the equalizer.