	US 12,456,972 B2
	Circuit assembly for limiting the gate current at a field-effect transistor
Sascha Krause, Berlin (DE)
Assigned to FERDINAND-BRAUN-INSTITUT GGMBH LEIBNIZ-INSTITUT FÜR HÖCHSTFREQUENZTECHNIK, Berlin (DE)
Appl. No. 17/998,410
Filed by FERDINAND-BRAUN-INSTITUT GGMBH LEIBNIZ-INSTITUT FÜR HÖCHSTFREQUENZTECHNIK, Berlin (DE)
PCT Filed May 5, 2021, PCT No. PCT/EP2021/061843 § 371(c)(1), (2) Date Nov. 10, 2022, PCT Pub. No. WO2021/228652, PCT Pub. Date Nov. 18, 2021.
Claims priority of application No. 10 2020 112 980.7 (DE), filed on May 13, 2020.
Prior Publication US 2023/0308087 A1, Sep. 28, 2023
Int. Cl. H03F 1/30 (2006.01); H03F 3/193 (2006.01); H03K 17/0812 (2006.01)

CPC H03K 17/08122 (2013.01) [H03F 3/193 (2013.01); H03F 2200/18 (2013.01); H03F 2200/294 (2013.01); H03F 2200/451 (2013.01)]

8 Claims

1. A circuit arrangement for limiting the gate current on afield effect transistor, FET, comprising a first FET and a DC supply network connected to a gate terminal of the first FET; the supply network providing a voltage V_ggto the gate terminal of the first FET via a first connection comprising a high impedance resistor R₁and a second FET connected in series therewith and having a gate terminal; the second FET having an ON state at a gate-source voltage of 0 V and having its gate terminal also connected to the gate terminal of the first FET via a second connection in parallel with the resistor R₁; wherein a voltage drop occurring across the resistor R₁results in increasing blocking of the second FET, wherein for RF decoupling the first connection and the second connection are connected to the gate terminal of the first FET via a common inductance L.