US 12,456,971 B2
Method and apparatus for limiting minority carrier injection
Rajiv Damodaran Prabha, Nashua, NH (US); and David Abramson, Stratham, NH (US)
Assigned to Allegro MicroSystems, LLC, Manchester, NH (US)
Filed by Allegro MicroSystems, LLC, Manchester, NH (US)
Filed on Nov. 30, 2023, as Appl. No. 18/524,664.
Prior Publication US 2025/0183884 A1, Jun. 5, 2025
Int. Cl. H03K 17/06 (2006.01); H03K 17/082 (2006.01); H03K 17/687 (2006.01)
CPC H03K 17/063 (2013.01) [H03K 17/0822 (2013.01); H03K 17/687 (2013.01); H03K 2217/0036 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A driver circuit comprising:
a substrate;
a first terminal;
a second terminal;
a switching circuit that is formed on the substrate, the switching circuit including a first switch and a second switch, the first switch having a first drain and a first source, the second switch having a second drain and a second source, the first drain being coupled to the first terminal, the first source being coupled to the second drain, the second source being coupled to ground, and the second terminal being coupled to the first source and the second drain;
an electrostatic discharge (ESD) diode that is formed on the substrate;
a trigger circuit that is formed on the substrate, the trigger circuit being configured to divert a first electrical current when the trigger circuit is activated, the first electrical current being diverted from the second terminal to the first terminal via the first switch; and
a detector transistor that is formed on the substrate, the detector transistor being configured to form a parasitic bipolar junction transistor (BJT) together with the substrate and the ESD diode, the parasitic BJT being configured to activate the trigger circuit when a second electrical current exceeds a first value, the second electrical current flowing from a collector of the parasitic BJT to an emitter of the parasitic BJT,
wherein the parasitic BJT includes, a first n-layer, a p-layer, and a second n-layer, the first n-layer being provided by a drain of the detector transistor, the p-layer being provided by the substrate, and the second n-layer being provided by a cathode of the ESD diode.