US 12,456,969 B2
Data detection on serial communication links
Vishal Varma, Fremont, CA (US); Dhaval H. Shah, Newark, CA (US); Jose A. Tierno, Menlo Park, CA (US); Sanjeev K. Maheshwari, Fremont, CA (US); and Sumeet Gupta, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Apr. 26, 2024, as Appl. No. 18/647,865.
Application 18/647,865 is a continuation of application No. 17/823,952, filed on Aug. 31, 2022, granted, now 12,028,075.
Claims priority of provisional application 63/365,431, filed on May 27, 2022.
Prior Publication US 2024/0283436 A1, Aug. 22, 2024
Int. Cl. H03K 5/08 (2006.01); H04L 25/06 (2006.01)
CPC H03K 5/082 (2013.01) [H04L 25/062 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a data rate detection circuit configured to:
detect that a communication link operates in a high-speed mode rather than in a low-speed mode, wherein, to detect that the communication link operates in the high-speed mode, the data rate detection circuit is configured to determine that a number of samples sampled during a reference time period satisfy a threshold value, the samples generated based on a signal that encodes a serial data stream and received on the communication link; and
activate a data rate detection signal indicating that the communication link operates in the high-speed mode, wherein the data rate detection signal is activated in response to a determination that the number of samples satisfy the threshold value; and
a receiver circuit that includes a plurality of subcircuits, wherein the receiver circuit is configured to;
generate the samples during the reference time period, the samples generated based on the signal; and
activate one or more of the plurality of subcircuits in response to activation of the data rate detection signal.