US 12,456,910 B2
Latch-up mitigated charge pump for high power supply rejection low-dropout regulator
Bibhu Prasad Das, Philadelphia, PA (US); Abhishek Bhat, Allentown, PA (US); Kadaba Lakshmikumar, Hillsborough, NJ (US); and Romesh Kumar Nandwana, Chapel Hill, NC (US)
Assigned to CISCO TECHNOLOGY, INC., San Jose, CA (US)
Filed by Cisco Technology, Inc., San Jose, CA (US)
Filed on Apr. 12, 2023, as Appl. No. 18/299,174.
Prior Publication US 2024/0348143 A1, Oct. 17, 2024
Int. Cl. H02M 1/00 (2007.01); H02M 3/07 (2006.01)
CPC H02M 1/0045 (2021.05) [H02M 3/073 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a pre-regulator circuit configured to receive an input voltage and to provide an internal regulated voltage, and to compare the internal regulated voltage with a voltage reference;
a pre-regulator control switch coupled to the pre-regulator circuit and configured to control operation of the pre-regulator circuit;
a voltage doubler comprising a cross-coupled pair of N-type metal oxide silicon (NMOS) transistors and a pair of charge pump capacitors, and a P-type metal oxide silicon (PMOS) switch circuit coupled to the cross-coupled pair of NMOS transistors, the PMOS switch circuit comprising PMOS transistor switches sharing a common Nwell node, the cross-coupled pair of NMOS transistors being connected to receive the internal regulated voltage from the pre-regulator circuit, wherein the voltage doubler is configured to produce a voltage doubler output voltage that is double the input voltage;
a clock buffer circuit coupled to the voltage doubler and to the pre-regulator circuit;
a logic gate coupled to the clock buffer circuit, the logic gate configured to receive a clock signal and a gating control signal as input; and
an NMOS transistor switch connected to the PMOS switch circuit and configured to receive the input voltage and to charge the Nwell node of the PMOS switch circuit.