| CPC H02M 1/0012 (2021.05) [B60L 53/22 (2019.02); H02J 7/0068 (2013.01); H02M 7/493 (2013.01); H02M 7/53873 (2013.01); H02J 2207/20 (2020.01)] | 37 Claims |

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1. A first multi-level inverter, the first multi-level inverter comprising:
a plurality of modules, each module comprising: at least two charge storage elements, a balancing circuit for equalizing individual voltages of the at least two charge storage elements within the same module, an H-bridge power stage with a power input provided by the at least two charge storage elements connected in series, wherein the H-bridge power stage, in turn, comprises a plurality of transistors configured to produce a differential output voltage from the module on two differential outputs, and a processing unit configured to control a state of the H-bridge power stage, wherein the processing unit further comprises a first communication interface;
at least one cascade inverter phase comprising at least two modules and two power terminals, wherein when more than one cascade inverter phase is present, each cascade inverter phase has the same number of modules, wherein the modules within the at least one cascade inverter phase are connected in series between the two power terminals using the differential outputs of each module;
a first control unit comprising: a processor configured to define the state of each H-bridge power stage within a respective module of the plurality of modules, and a second communication interface operatively connected to at least one individual bus; and
a communication network comprising the at least one individual bus common to at least two modules operatively connected thereto, wherein the at least one individual bus is configured to facilitate bidirectional data transfer between the first communication interface of the plurality of modules and the second communication interface of the first control unit, wherein the first control unit is further configured to operatively communicate the defined state of the H-bridge power stage within the respective module to the plurality of modules, wherein each module is assigned an address which is unique within the individual bus associated therewith, and wherein the plurality of modules are further configured to communicate information about the respective state of their charge storage elements to the first control unit.
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