US 12,456,860 B2
Clamp circuit
Hong-Sheng Wang, Taoyuan (TW); Chang-Jing Yang, Taoyuan (TW); Wei-Hsiang Chao, Taoyuan (TW); and Ying-Chen Liu, Taoyuan (TW)
Assigned to ANCORA SEMICONDUCTORS INC., Taoyuan (TW)
Filed by Ancora Semiconductors Inc., Taoyuan (TW)
Filed on Nov. 30, 2023, as Appl. No. 18/524,962.
Prior Publication US 2025/0183657 A1, Jun. 5, 2025
Int. Cl. H02H 9/04 (2006.01)
CPC H02H 9/046 (2013.01) 20 Claims
OG exemplary drawing
 
1. A clamp circuit comprising:
a major Gallium Nitride (GaN) transistor comprising a major gate, a major drain, and a major source coupled to a first node;
a miller GaN transistor comprising a miller gate coupled to a second node, a miller drain coupled to the major gate, and a miller source coupled to the first node;
a capacitor circuit coupled between the major drain and the second node; and
a protection circuit coupled between the second node and the first node, wherein the protection circuit comprises:
a first resistor comprising a first terminal coupled to the second node and a second terminal coupled to the first node;
a first capacitor comprising a first terminal coupled to the second node and a second terminal coupled to the first node;
a first diode comprising a first anode coupled to the second node and a first cathode; and
a second diode comprising a second anode coupled to the first node and a second cathode coupled to the first cathode.