US 12,456,711 B2
Semiconductor package
Chihong Shin, Suwon-si (KR); and Raehyung Do, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 13, 2023, as Appl. No. 18/096,859.
Claims priority of application No. 10-2022-0073630 (KR), filed on Jun. 16, 2022.
Prior Publication US 2023/0411354 A1, Dec. 21, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/3121 (2013.01); H01L 23/49838 (2013.01); H01L 24/06 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/06135 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/48471 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/49051 (2013.01); H01L 2224/49096 (2013.01); H01L 2224/49175 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01)] 20 Claims
OG exemplary drawing
 
18. A semiconductor package comprising:
a package substrate comprising substrate pads disposed in rows parallel to each other in a first direction on a surface of the package substrate;
a semiconductor chip comprising chip pads disposed in the first direction on the surface of the package substrate and spaced apart from the substrate pads; and
bonding wires connecting the chip pads and the substrate pads,
wherein the bonding wires comprise first bonding wires and second bonding wires alternately connected to the substrate pads in the first direction,
wherein the first bonding wires are connected to the substrate pads at a first angle less than a right angle with respect to a direction of the semiconductor chip,
wherein a position at which the first bonding wires contact the substrate pads is closer to the semiconductor chip than a position at which the second bonding wires contact the substrate pads is to the semiconductor chip, and
wherein the second bonding wires are connected to the substrate pads at a second angle less than the first angle with respect to the direction of the semiconductor chip.