US 12,456,710 B2
Semiconductor device
Satoru Itakura, Machida Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Aug. 19, 2022, as Appl. No. 17/891,881.
Claims priority of application No. 2022-034338 (JP), filed on Mar. 7, 2022.
Prior Publication US 2023/0282616 A1, Sep. 7, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 25/0652 (2013.01) [H01L 25/18 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a wiring board having a surface;
a chip stack disposed above the surface and having a first semiconductor chip;
a second semiconductor chip disposed between the surface and the chip stack;
a spacer disposed between the surface and the first semiconductor chip, the spacer surrounding the second semiconductor chip along the surface, and the spacer containing a material higher in thermal conductivity than silicon; and
a sealing insulation layer covering the chip stack,
wherein
the spacer has a passage connecting a first region outside the spacer on the surface and a second region inside the spacer on the surface,
the sealing insulation layer extends through the passage and covers the second semiconductor chip, and
the passage is defined by a second depression facing on the chip stack.