US 12,456,708 B2
Semiconductor packages
Sang Sub Song, Suwon-si (KR); Seongho Yoon, Suwon-si (KR); and Ki-Hong Jeong, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 22, 2023, as Appl. No. 18/188,368.
Claims priority of application No. 10-2022-0096391 (KR), filed on Aug. 2, 2022.
Prior Publication US 2024/0047409 A1, Feb. 8, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 23/528 (2006.01); H01L 25/16 (2023.01)
CPC H01L 24/73 (2013.01) [H01L 23/4952 (2013.01); H01L 23/5283 (2013.01); H01L 24/85 (2013.01); H01L 25/16 (2013.01); H01L 2224/73207 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06517 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package substrate having a first surface and a second surface that are opposite to each other;
a control chip on the first surface of the package substrate;
a mode selection connection terminal between the control chip and the package substrate;
a stack structure spaced apart from the control chip on the first surface of the package substrate, the stack structure comprising a plurality of stacked memory chips;
a first power pad adjacent the first surface of the package substrate;
a wire pad adjacent the first surface of the package substrate and spaced apart from the first power pad;
a first external connection terminal on the second surface of the package substrate; and
a first interconnection line and a second interconnection line in the package substrate,
wherein the first power pad and the wire pad are spaced apart from the control chip,
wherein the first interconnection line electrically connects the first power pad to the first external connection terminal,
wherein the second interconnection line electrically connects the wire pad to the mode selection connection terminal, and
wherein the first external connection terminal is configured to provide a ground voltage or a power voltage to the first power pad.