	US 12,456,701 B2
	Efficient integration of a first substrate without solder bumps with a second substrate having solder bumps
Edward Preisler, San Clemente, CA (US); and Zhirong Tang, Lake Oswego, OR (US)
Assigned to Newport Fab, LLC, Newport Beach, CA (US)
Filed by Newport Fab, LLC, Newport Beach, CA (US)
Filed on Oct. 17, 2022, as Appl. No. 17/967,107.
Prior Publication US 2024/0128209 A1, Apr. 18, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01)

CPC H01L 24/05 (2013.01) [H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/05005 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05669 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/16012 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2924/3701 (2013.01)]

20 Claims

1. A method of forming a semiconductor structure, said method comprising:

providing a first substrate without a solder bump;

forming a solder bump receiving metal over a top interconnect metal of said first substrate, said solder bump receiving metal being selected from the group consisting of platinum, a platinum alloy, nickel, and a nickel alloy;

forming a passivation layer, wherein said passivation layer is not situated under any portion of said solder bump receiving metal;

forming a window exposing a portion of said solder bump receiving metal;

wherein after processing of said first substrate, said exposed portion of said solder bump receiving metal is capable to electrically and directly mechanically connect to a second substrate.