US 12,456,697 B2
Multilayer wiring substrate and module having multilayer wiring substrate
Noriko Kano, Tokyo (JP); Tomoyuki Shirasaki, Tokyo (JP); and Susumu Maniwa, Tokyo (JP)
Assigned to TOPPAN INC., Tokyo (JP)
Filed by TOPPAN INC., Tokyo (JP)
Filed on Nov. 17, 2022, as Appl. No. 17/988,847.
Application 17/988,847 is a continuation of application No. PCT/JP2021/016277, filed on Apr. 22, 2021.
Claims priority of application No. 2020-097728 (JP), filed on Jun. 4, 2020.
Prior Publication US 2023/0111374 A1, Apr. 13, 2023
Int. Cl. H01L 23/66 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H03H 3/00 (2006.01); H03H 7/01 (2006.01); H05K 1/16 (2006.01)
CPC H01L 23/66 (2013.01) [H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H03H 3/00 (2013.01); H03H 7/0115 (2013.01); H05K 1/162 (2013.01); H05K 1/165 (2013.01); H01L 2223/6672 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A multilayer wiring substrate comprising: a core substrate, and capacitors installed therein, comprising:
a first capacitor that is at least one of the capacitors, the first capacitor including a lower electrode, a dielectric layer, and an upper electrode, the lower electrode being located closer to the core substrate than the dielectric layer and the upper electrode are, the upper electrode being located farther away from the core substrate than the dielectric layer and the lower electrode are,
the lower electrode is entirely disposed on the core substrate,
the upper electrode has a first portion and a second portion, the first portion overlapping the dielectric layer and the lower electrode to serve as the first capacitor, the second portion extending from the first portion, the second portion being disposed on a surface of the core substrate on which the lower electrode is arranged,
the second portion of the upper electrode includes a terminal;
an interlayer via is formed in an insulating resin layer formed on the upper electrode as a portion for electrically connecting adjacent conductor layers; and
the interlayer via is formed on the upper electrode, the interlayer via connects the second portion of the upper electrode to a third conductive layer formed on the insulating resin layer.