US 12,456,691 B2
Semiconductor device
Yuji Ishimatsu, Kyoto (JP); Kenji Hama, Kyoto (JP); and Hideo Hara, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Appl. No. 17/910,483
Filed by ROHM CO., LTD., Kyoto (JP)
PCT Filed Feb. 22, 2021, PCT No. PCT/JP2021/006625
§ 371(c)(1), (2) Date Sep. 9, 2022,
PCT Pub. No. WO2021/187018, PCT Pub. Date Sep. 23, 2021.
Claims priority of application No. 2020-048942 (JP), filed on Mar. 19, 2020.
Prior Publication US 2023/0163078 A1, May 25, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/15 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/5386 (2013.01) [H01L 23/15 (2013.01); H01L 23/3121 (2013.01); H01L 23/49811 (2013.01); H01L 24/48 (2013.01); H01L 25/18 (2013.01); H01L 2224/48175 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate having a substrate obverse face and a substrate reverse face oriented in opposite directions to each other in a thickness direction;
a conductive section formed of a conductive material and located on the substrate obverse face, the conductive section including a first section and a second section spaced apart from each other;
a sealing resin covering at least a part of the substrate and an entirety of the conductive section; and
a conductive section wire conductively bonded to the first section and the second section,
wherein the conductive section includes a first wiring connected to the first section, and a third section connected to the first wiring.