US 12,456,687 B2
Three-dimensional memory device with source line isolation and method of making the same
Ramy Nashed Bassely Said, San Jose, CA (US); Jiahui Yuan, San Francisco, CA (US); and Lito De La Rama, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Sep. 23, 2022, as Appl. No. 17/934,685.
Prior Publication US 2024/0105623 A1, Mar. 28, 2024
Int. Cl. H01L 23/535 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H01L 23/535 (2013.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a source layer comprising at least one doped semiconductor material;
a source isolation dielectric structure laterally extending along a first horizontal direction and laterally separating the source layer into first source layer portion and a second source layer portion which is electrically isolated from the first source layer portion;
alternating stacks of insulating layers and electrically conductive layers located over the source layer, extending along the first horizontal direction and laterally spaced apart from each other along a second horizontal direction by at least one first backside trench that is filled with a respective first backside trench fill structure that comprises a respective first backside contact via structure contacting the source layer, and at least one second backside trench that is filled with a respective second backside trench fill structure that comprises a respective second dummy backside contact via structure contacting the source isolation dielectric structure;
memory openings, wherein each of the memory openings vertically extends through a respective one of the alternating stacks; and
memory opening fill structures located in the memory openings and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel, wherein a sidewall of the respective vertical semiconductor channel is in contact with the source layer.