US 12,456,686 B2
Three-dimensional memory device with multilevel drain-select electrodes and methods for forming the same
Akihiro Tobioka, Yokkaichi (JP); and Satoshi Shimizu, Yokkaichi (JP)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Feb. 28, 2022, as Appl. No. 17/682,466.
Application 17/682,466 is a continuation in part of application No. 17/241,321, filed on Apr. 27, 2021, granted, now 12,010,835.
Prior Publication US 2022/0344266 A1, Oct. 27, 2022
Int. Cl. H01L 23/535 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H01L 23/535 (2013.01) [H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers, wherein the electrically conductive layers comprise word-line-level electrically conductive layers and drain-select-level electrically conductive layers located above the word-line-level electrically conductive layers;
memory opening fill structures vertically extending through the alternating stack in a memory array region in which each layer within the alternating stack is present, wherein each of the memory opening fill structures comprises a vertical semiconductor channel and a memory film; and
drain-select-level contact via structures,
wherein:
a first one of the drain-select level contact via structures directly contacts at least a first two of the drain-select-level electrically conductive layers that are vertically spaced apart from each other; and
a second one of the drain-select level contact via structures directly contacts at least a second two of the drain-select-level electrically conductive layers that are vertically spaced apart from each other and which are located below the at least the first two of the drain-select-level electrically conductive layers.