US 12,456,683 B2
Layout of conductive vias for semiconductor device
Kayoko Shibata, Tokyo (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Feb. 4, 2022, as Appl. No. 17/665,367.
Prior Publication US 2023/0253323 A1, Aug. 10, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/50 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10D 89/10 (2025.01)
CPC H01L 23/5286 (2013.01) [H01L 23/481 (2013.01); H01L 25/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06544 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory array region;
a peripheral region adjacent to the memory array region;
a plurality of power vias in the peripheral region configured to provide one or more power supply voltages from an interface chip; and
one or more wirings in the peripheral region, a first wiring of the one or more wirings adjacent to the memory array extending in a first direction,
wherein one or more power vias of the plurality of power vias are disposed through a respective wiring of the one or more wirings, and wherein the one or more power vias are along a second wiring of the one or more wirings, the second wiring extending from the peripheral region to the memory array region in a second direction perpendicular to the first direction.