US 12,456,678 B2
Methods for generating a circuit with high density routing layout
Wei-An Lai, Hsinchu (TW); Shih-Wei Peng, Hsinchu (TW); Wei-Cheng Lin, Taichung (TW); and Jiann-Tyng Tzeng, Hinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 8, 2024, as Appl. No. 18/437,130.
Application 18/437,130 is a division of application No. 17/242,056, filed on Apr. 27, 2021, granted, now 11,923,297.
Prior Publication US 2024/0178139 A1, May 30, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); G06F 30/31 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H01L 23/528 (2013.01) [G06F 30/394 (2020.01); H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0184 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/856 (2025.01); G06F 30/31 (2020.01); G06F 30/398 (2020.01)] 15 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, comprising:
forming a gate structure on a substrate that is located at a back side of the semiconductor structure;
forming a plurality of first metal lines formed in a first dielectric layer below the gate structure, wherein the plurality of first metal lines is at a back side of a standard cell;
forming at least one first via in a second dielectric layer that is between the gate structure and the first dielectric layer, wherein each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines;
forming a plurality of second metal lines in a third dielectric layer over the gate structure, wherein the plurality of second metal lines is at a front side of the standard cell, wherein the standard cell is a device with a plurality of input/output (I/O) pins;
routing at least one first pin of the plurality of I/O pins from the back side of the standard cell, wherein the at least one first pin toggles between a power supply voltage level and a ground voltage level when the device is powered on; and
routing at least one second pin of the plurality of I/O pins from the front side of the standard cell, wherein the at least one second pin toggles between the power supply voltage level and the ground voltage level when the device is powered on.