US 12,456,677 B2
Via landing on first and second barrier layers to reduce cleaning time of conductive structure
Te-Hsien Hsieh, Kaohsiung (TW); Yu-Hsing Chang, Taipei (TW); and Yi-Min Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 18, 2023, as Appl. No. 18/353,997.
Application 18/353,997 is a division of application No. 17/197,381, filed on Mar. 10, 2021, granted, now 11,776,901.
Prior Publication US 2023/0361024 A1, Nov. 9, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76814 (2013.01); H01L 23/53223 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a conductive structure arranged within a substrate or a first dielectric layer;
a first barrier layer arranged on outermost sidewalls and a bottom surface of the conductive structure;
a second barrier layer arranged on outer surfaces of the first barrier layer, wherein the second barrier layer separates the first barrier layer from the substrate or the first dielectric layer;
a second dielectric layer arranged over the substrate or the first dielectric layer; and
a via structure extending through the second dielectric layer, arranged directly over topmost surfaces of the first and second barrier layers, and electrically coupled to the conductive structure through the first and second barrier layers, wherein the via structure has a smaller width than the conductive structure as viewed in a cross-sectional view.