US 12,456,676 B2
Semiconductor device including first and second transistor channels
Gerben Doornbos, Kessel-Lo (BE); and Mauricio Manfrini, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed on Apr. 20, 2022, as Appl. No. 17/725,015.
Prior Publication US 2023/0343696 A1, Oct. 26, 2023
Int. Cl. H01L 23/52 (2006.01); H01L 23/522 (2006.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10D 30/01 (2025.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01)
CPC H01L 23/5226 (2013.01) [H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10D 30/0411 (2025.01); H10D 30/0413 (2025.01); H10D 30/68 (2025.01); H10D 30/6894 (2025.01); H10D 30/69 (2025.01); H10D 30/699 (2025.01); H10D 64/035 (2025.01); H10D 64/037 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a memory structure, comprising:
a first transistor channel;
a gate structure, comprising a control gate, overlying the first transistor channel; and
a second transistor channel overlying the gate structure, wherein the control gate is configured to control the first transistor channel and the second transistor channel.