US 12,456,674 B2
Leadframeless electrically isolated power semiconductor package
Tiburcio Maldo, Batangas (PH); Robert Ebido, Cavite (PH); Arnel Deveza, Laguna (PH); Jeff Grozen, Muntinlupa (PH); and Roger Cadut, Laguna (PH)
Assigned to Littelfuse, Inc., Rosemont, IL (US)
Filed by Littelfuse, Inc., Chicago, IL (US)
Filed on May 23, 2023, as Appl. No. 18/200,853.
Prior Publication US 2024/0395692 A1, Nov. 28, 2024
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/60 (2006.01); H01L 21/67 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 23/433 (2006.01); H01L 23/495 (2006.01)
CPC H01L 23/49861 (2013.01) [H01L 21/565 (2013.01); H01L 23/3735 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/29139 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/10272 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A power semiconductor package (PSP) comprising:
a substrate comprising alternating layers of copper and silicon nitride;
a plurality of copper leads coupled to the substrate using active metal brazing, wherein the copper leads are not part of a leadframe; and
a die coupled to the substrate using silver sintered paste;
an encapsulant to encase the substrate and the die, wherein a portion of the plurality of copper leads are external to the encapsulant;
a first copper layer having a first dimension;
a second copper layer having a second dimension;
a first ceramic layer sandwiched between the first copper layer and the second copper layer, the first ceramic layer having a third dimension;
a third copper layer having the first dimension; and
a second ceramic layer sandwiched between the second copper layer and the third copper layer, the second ceramic layer having the third dimension.