US 12,456,673 B2
Flip chip package and substrate thereof
Chun-Te Lee, Hsinchu County (TW); Chih-Ming Peng, Taichung (TW); Pi-Yu Peng, Hsinchu County (TW); Hui-Yu Huang, Hsinchu (TW); and Yin-Chen Lin, Miaoli County (TW)
Assigned to CHIPBOND TECHNOLOGY CORPORATION, Hsinchu (TW)
Filed by CHIPBOND TECHNOLOGY CORPORATION, Hsinchu (TW)
Filed on Jun. 27, 2023, as Appl. No. 18/214,572.
Claims priority of application No. 111125640 (TW), filed on Jul. 8, 2022.
Prior Publication US 2024/0014118 A1, Jan. 11, 2024
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 2224/13013 (2013.01); H01L 2224/14163 (2013.01); H01L 2224/16227 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A flip chip package comprising:
a chip including a plurality of first bumps, a plurality of second bumps and at least one identification bump; and
a substrate including:
a light-transmissive carrier including a first surface and a second surface, a chip-mounting area and a circuit area are defined on the first surface, a supportive area opposite to the chip-mounting area is defined on the second surface;
a patterned metal layer disposed on the chip-mounting area and the circuit area and including a plurality of first lines, a plurality of second lines, at least one identification line and a first dummy line, a first lead of each of the plurality of first lines, a second lead of each of the plurality of second lines, an identification lead of the at least one identification line and the first dummy line are located on the chip-mounting area, the second lead is adjacent to the first lead, the identification lead is located on one side of the first dummy line and projects a lead shadow on the second surface, the first dummy line projects a first measurement shadow on the second surface, each of the plurality of first bumps is bonded to the first lead of one of the plurality of first lines, each of the plurality of second bumps is bonded to the second lead of one of the plurality of second lines, the at least one identification bump is bonded to the identification lead, wherein the first lead, the second lead, the identification lead, the plurality of first bumps, the plurality of second bumps and the at least one identification bump are configured to be covered by the chip, wherein the identification bump projects a second measurement shadow on the second surface, and a width of the lead shadow is less than a width of the second measurement shadow in a direction parallel to a first imaginary line; and
a supportive layer disposed on the supportive area and configured to cover shadows of the first lead, the second lead, the plurality of first bumps and the plurality of second bumps which are projected on the second surface, wherein the first and second measurement shadows are visible from an opening of the supportive layer, and there is a first gap between the first and second measurement shadows in the direction parallel to the first imaginary line.