US 12,456,672 B2
Packaging substrate having element group in cavity unit and semiconductor device comprising the same
Sungjin Kim, Suwanee, GA (US); Youngho Rho, Daejeon (KR); Jincheol Kim, Hwaseong-si (KR); and Byungkyu Jang, Suwon-Si (KR)
Assigned to Absolics Inc.
Filed by ABSOLICS INC., Covington, GA (US)
Filed on Mar. 1, 2023, as Appl. No. 18/176,975.
Application 18/176,975 is a continuation of application No. 17/433,349, granted, now 11,652,039, previously published as PCT/KR2020/003476, filed on Mar. 12, 2020.
Claims priority of provisional application 62/826,144, filed on Mar. 29, 2019.
Claims priority of provisional application 62/826,122, filed on Mar. 29, 2019.
Claims priority of provisional application 62/825,216, filed on Mar. 28, 2019.
Claims priority of provisional application 62/817,027, filed on Mar. 12, 2019.
Claims priority of provisional application 62/816,984, filed on Mar. 12, 2019.
Claims priority of provisional application 62/817,003, filed on Mar. 12, 2019.
Prior Publication US 2023/0207442 A1, Jun. 29, 2023
Int. Cl. H01L 23/498 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49894 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A packaging substrate comprising:
a core layer, and an upper layer disposed on the core layer,
wherein the core layer comprises a glass substrate and a core via,
wherein the glass substrate has a first surface and a second surface that face each other,
wherein the glass substrate comprises a first area with a first thickness, and a second area adjacent to the first area and having a second thickness that is thinner than the first thickness,
wherein a plurality of core vias penetrate through the glass substrate in a thickness direction,
wherein the core layer further comprises a core distribution layer disposed on a surface of the glass substrate or in the core via,
wherein at least a portion of the core distribution layer electrically connects an electrically conductive layer on the first surface and an electrically conductive layer on the second surface through the core via,
wherein the upper layer is disposed on the first surface and comprises an electrically conductive layer configured to electrically connect the core distribution layer to an external semiconductor element unit;
wherein a cavity unit is disposed on or beneath the second area, the cavity unit comprising:
an inner space,
a cavity distribution layer electrically connected to the core distribution layer, and
an element group disposed in the inner space, and
wherein the element group comprises a cavity element insulating layer and a cavity element embedded in the cavity element insulating layer.