	US 12,456,661 B2
	Semiconductor structure having a silicon active layer formed over a SiGe etch stop layer and an insulating layer with a through silicon via (TSV) passed therethrough
Yu-Hung Cheng, Tainan (TW); Shih-Pei Chou, Tainan (TW); Yeur-Luen Tu, Taichung (TW); Alexander Kalnitsky, San Francisco, CA (US); Tung-I Lin, Tainan (TW); and Wei-Li Chen, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jun. 11, 2021, as Appl. No. 17/346,186.
Application 17/346,186 is a continuation of application No. 15/130,182, filed on Apr. 15, 2016, granted, now 11,049,797.
Prior Publication US 2021/0305131 A1, Sep. 30, 2021
Int. Cl. H01L 23/48 (2006.01); H01L 21/20 (2006.01); H01L 21/306 (2006.01); H01L 21/683 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H10D 86/01 (2025.01)

CPC H01L 23/481 (2013.01) [H01L 21/2007 (2013.01); H01L 21/30604 (2013.01); H01L 21/6835 (2013.01); H01L 21/76256 (2013.01); H01L 21/76829 (2013.01); H01L 21/76898 (2013.01); H10D 86/0214 (2025.01); H01L 2221/68359 (2013.01)]

20 Claims

1. A semiconductor structure, comprising:

an epitaxial etch selectivity layer;

a semiconductor device layer in contact with and over the epitaxial etch selectivity layer, wherein the semiconductor device layer includes an active region of a semiconductor device in a silicon epitaxial layer and metallization layers, wherein the metallization layers are disposed on a same side of the silicon epitaxial layer, the metallization layers include a first horizontal interconnect layer and a second horizontal interconnect layer, the second horizontal interconnect layer is further away from the silicon epitaxial layer than the first horizontal interconnect layer, and the first horizontal interconnect layer electrically connects to a transistor in the active region through a vertical interconnect;

an insulating layer over a first side of the semiconductor device layer, the insulating layer being in contact with the epitaxial etch selectivity layer, and the active region being between the insulating layer and the metallization layers;

a first through-silicon via (TSV) passing through the insulating layer, the epitaxial etch selectivity layer and extending from a first surface of the insulating layer into the semiconductor device layer, wherein a top surface of the first TSV is substantially aligned with the first surface of the insulating layer;

wherein the epitaxial etch selectivity layer and the semiconductor device layer are in contact with a sidewall of the first TSV, the epitaxial etch selectivity layer fully covers the first side of the semiconductor device layer except at the first TSV, and a bottom surface of the first TSV physically contacts a first conductive line of the second horizontal interconnect layer of the metallization layers; and

a second TSV extending from the first surface of the insulating layer to the second horizontal interconnect layer, wherein a bottom surface of the second TSV physically contacts a second conductive line of the second horizontal interconnect layer,

wherein a thickness of the silicon epitaxial layer is about half a thickness of the epitaxial etch selectivity layer,

wherein the epitaxial etch selectivity layer includes carbon, phosphorus, gallium, nitrogen, or arsenic doped into silicon.

9. A semiconductor structure, comprising:

an epitaxial etch stop layer, having a thickness about 200 nm;

a silicon epitaxial layer in contact with and over the epitaxial etch stop layer, wherein the epitaxial etch stop layer includes silicon germanium (SiGe) with a lattice constant greater than a material made of the silicon epitaxial layer;

an active region of a semiconductor device in the silicon epitaxial layer;

an ILD layer over the silicon epitaxial layer, wherein the ILD layer includes metallization layers, and the silicon epitaxial layer and the ILD layer together form a device layer including a transistor, wherein the metallization layers are disposed on a same side of the silicon epitaxial layer, the metallization layers include a first horizontal interconnect layer and a second horizontal interconnect layer, the second horizontal interconnect layer is further away from the transistor than the first horizontal interconnect layer, and the first horizontal interconnect layer electrically connects to the transistor through a vertical interconnect;

an oxide layer over a first side of the device layer, the oxide layer being in contact with the epitaxial etch stop layer, and the active region being between the oxide layer and the metallization layers, wherein the oxide layer includes a first surface away from the epitaxial etch stop layer;

a first through-silicon via (TSV) passing through the oxide layer, the epitaxial etch stop layer, the silicon epitaxial layer and extending into the ILD layer, wherein a top surface of the first TSV is horizontally aligned with the first surface of the oxide layer, and a bottom surface of the first TSV physically contacts a first conductive line of the second horizontal interconnect layer of the metallization layers; and

a second TSV extending from the first surface of the oxide layer to the second horizontal interconnect layer, wherein a bottom surface of the second TSV physically contacts a second conductive line of the second horizontal interconnect layer,

wherein a thickness of the silicon epitaxial layer is about half the thickness of the epitaxial etch stop layer,

wherein a combined thickness of the silicon epitaxial layer and the ILD layer ranges from 1.5 μm to 5 μm.

16. A semiconductor structure, comprising:

an epitaxial etch selectivity layer having a thickness of about 200 nm;

a semiconductor device layer including a transistor in contact with and over the epitaxial etch selectivity layer, wherein the semiconductor device layer includes an active region in a silicon epitaxial layer of a semiconductor device and metallization layers, wherein the metallization layers include a first horizontal interconnect layer and a second horizontal interconnect layer, the first horizontal interconnect layer is closer to the epitaxial etch selectivity layer than the second horizontal interconnect layer, and the first horizontal interconnect layer electrically connects to the transistor through a vertical interconnect;

a dielectric layer disposed over the insulating layer, wherein an interface is defined between the dielectric layer and the insulating layer;

a first through-silicon via (TSV) passing through the insulating layer, the epitaxial etch selectivity layer and extending into the semiconductor device layer, wherein an entirety of the first TSV is between the interface and one of the metallization layers, and the first TSV is separated from conductive features in the first horizontal interconnect layer and physically contacts a conductive feature in the second horizontal interconnect layer;

wherein the epitaxial etch selectivity layer gradually decreases a concentration of germanium therein from about 20% to about 30% within 40 nm distanced from an interface between the epitaxial etch selectivity layer and the semiconductor device to about 0% around the interface between the epitaxial etch selectivity layer and the semiconductor device layer; and

a second TSV passing through the insulating layer, the epitaxial etch selectivity layer, wherein a bottom surface of the second TSV physically contacts another conductive feature in the second horizontal interconnect layer,

wherein a thickness of the silicon epitaxial layer is about half a thickness of the epitaxial etch selectivity layer,

wherein the epitaxial etch selectivity layer includes carbon, phosphorus, gallium, nitrogen, or arsenic doped into silicon,

wherein the device layer includes an ILD layer, and a combined thickness of the silicon epitaxial layer and the ILD layer ranges from 1.5 μm to 5 μm.