US 12,456,660 B2
Semiconductor package
Yongkwan Lee, Hwaseong-si (KR); Seunghwan Kim, Asan-si (KR); Jungjoo Kim, Hwaseong-si (KR); Jongwan Kim, Asan-si (KR); and Junwoo Park, Asan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 18, 2022, as Appl. No. 17/747,131.
Claims priority of application No. 10-2021-0121172 (KR), filed on Sep. 10, 2021.
Prior Publication US 2023/0082412 A1, Mar. 16, 2023
Int. Cl. H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01); H01L 23/00 (2006.01)
CPC H01L 23/3677 (2013.01) [H01L 23/3675 (2013.01); H01L 23/481 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 25/0655 (2013.01); H01L 25/162 (2013.01); H01L 25/165 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package substrate;
an interposer arranged on the package substrate and comprising a plurality of lower pads and a lower protective layer that comprises a plurality of openings exposing the plurality of lower pads;
a plurality of conductive connectors connecting the package substrate to the interposer;
a semiconductor chip arranged between the package substrate and the interposer;
a plurality of cooling patches arranged between the semiconductor chip and the interposer and having cylindrical shapes; and
an insulation filler directly contacting side surfaces of the plurality of conductive connectors, a side surface of the semiconductor chip, and side surfaces of the plurality of cooling patches,
wherein upper surfaces of the plurality of cooling patches are coplanar with an upper surface of the insulation filler,
wherein lower surfaces of the plurality of cooling patches directly contact an upper surface of the semiconductor chip,
wherein a height of each of the plurality of cooling patches is less than or equal to a diameter of each of the plurality of cooling patches,
wherein thermal conductivity of each of the plurality of cooling patches is greater than thermal conductivity of the lower protective layer,
wherein the thermal conductivity of each of the plurality of cooling patches ranges from 10 W/(m·K) to 100 W/(m·K),
wherein the diameter of each of the plurality of cooling patches ranges from 50 μm to 200 μm, and
wherein the height of each of the plurality of cooling patches ranges from 10 μm to 100 μm.