US 12,456,656 B2
Multichip interconnect package
Akihiro Horibe, Yokohama (JP); Toyohiro Aoki, Yokohama (JP); Chinami Marushima, Urayasu (JP); Takahito Watanabe, Yokohama (JP); and Takashi Hisada, Hachiouji (JP)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 11, 2022, as Appl. No. 17/942,149.
Application 17/942,149 is a continuation in part of application No. 17/704,061, filed on Mar. 25, 2022.
Prior Publication US 2023/0307307 A1, Sep. 28, 2023
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/3185 (2013.01) [H01L 21/563 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An interconnected semiconductor subassembly structure, comprising:
an interconnect structure;
a first semiconductor die bonded to a first portion of a top surface of the interconnect structure;
a second semiconductor die bonded to a second portion of the top surface of the interconnect structure; and
a resin layer located within at least a first portion of a gap between the first semiconductor die and the second semiconductor die, wherein a top surface and a bottom surface of the resin layer located within the at least first portion of the gap each have a concave meniscus shape.