US 12,456,655 B2
Passivation layer for a semiconductor device and method for manufacturing the same
Li Chun Liu, Kaohsiung (TW); Chun Tang Wang, Tainan (TW); Chih Hung Wang, Taipei (TW); Ching Feng Lee, Tainan (TW); and Yu-Lung Yeh, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 24, 2023, as Appl. No. 18/173,837.
Application 18/173,837 is a continuation of application No. 17/248,879, filed on Feb. 11, 2021, granted, now 11,594,459.
Prior Publication US 2023/0197550 A1, Jun. 22, 2023
Int. Cl. H01L 23/31 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/3171 (2013.01) [H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 23/528 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an ultra-thick metal (UTM) structure on a substrate;
a first passivation oxide consisting of an unbias film and a first bias film; and
a second passivation oxide, consisting of a second bias film, on the first bias film, wherein, at a top of the UTM structure, a thickness of the second bias film is greater than a thickness of the first bias film.