US 12,456,654 B2
Power semiconductor modules
Marco Ludwig, Wickede (DE); and Guido Boenig, Warstein (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Sep. 12, 2022, as Appl. No. 17/942,317.
Claims priority of application No. 21196284 (EP), filed on Sep. 13, 2021.
Prior Publication US 2023/0077384 A1, Mar. 16, 2023
Int. Cl. H01L 23/16 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/053 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/16 (2013.01) [H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 23/053 (2013.01); H01L 23/49811 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73215 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A power semiconductor module arrangement comprising:
at least one substrate comprising a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer;
at least one semiconductor body arranged on the first metallization layer;
a cover;
a housing at least partly enclosing the substrate, the housing comprising sidewalls; and
at least one press-on pin, wherein
each press-on pin is arranged either on the substrate or on one of the at least one semiconductor body and extends from the substrate or the respective semiconductor body in a vertical direction that is perpendicular to a top surface of the substrate,
each press-on pin is mechanically coupled to at least one sidewall of the housing by means of a bar, each bar extending horizontally between the respective press-on pin and sidewall, and parallel to the top surface of the substrate,
the cover is arranged on the sidewalls, thereby closing the housing in the vertical direction,
the cover exerts pressure on the press-on pin in the vertical direction, thereby pressing the press-on pin onto the substrate or onto the respective semiconductor body.