US 12,456,650 B2
Semiconductor device and method for manufacturing the same
Kyung Wook Kim, Hwaseong-si (KR); Seung Yong Yoo, Incheon (KR); Eui Bok Lee, Seoul (KR); Jin Nam Kim, Anyang-si (KR); and Eun-Ji Jung, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 21, 2022, as Appl. No. 17/991,090.
Claims priority of application No. 10-2022-0002448 (KR), filed on Jan. 7, 2022.
Prior Publication US 2023/0282512 A1, Sep. 7, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 23/535 (2006.01)
CPC H01L 21/76844 (2013.01) [H01L 21/76846 (2013.01); H01L 21/76865 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a lower line structure;
an upper interlayer insulating film provided on the lower line structure and having an upper line trench formed therein, wherein the upper line trench comprises an upper wiring line trench and an upper via trench extending from the upper wiring line trench to the lower line structure; and
an upper line structure provided in the upper line trench, wherein the upper line structure comprises an upper barrier film and an upper filling film,
wherein the upper filling film comprises a first sub-filling film in contact with the upper interlayer insulating film, and a second sub-filling film provided on the first sub-filling film,
wherein the first sub-filling film is a single film which fills an entirety of the upper via trench, covers at least a portion of a bottom surface of the upper wiring line trench, and extends between the upper interlayer insulating film and the upper barrier film to a sidewall of the upper line trench, and
wherein the upper barrier film is in contact with the upper interlayer insulating film, and is provided between the second sub-filling film and the upper interlayer insulating film.